Interrupt Clear-Enable Registers (Nvic_Icerx) - ST STM32F4 Series Programming Manual

Core peripherals
4.3.3

Interrupt clear-enable registers (NVIC_ICERx)

Address offset: 0x00 - 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
The ICER0-ICER2 registers disable interrupts, and show which interrupts are enabled.
31 30 29 28
rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:0 CLRENA: Interrupt clear-enable bits.
Write:
Read:
210/260
27 26 25
rc_w1 rc_w1 rc_w1
11 10 9
rc_w1 rc_w1 rc_w1
0: No effect
1: Disable interrupt
0: Interrupt disabled
1: Interrupt enabled.
24 23 22
CLRENA[31:16]
rc_w1 rc_w1 rc_w1
8 7 6
CLRENA[15:0]
rc_w1 rc_w1 rc_w1
DocID022708 Rev 6
21 20 19 18
rc_w1 rc_w1 rc_w1 rc_w1
5 4 3
rc_w1 rc_w1 rc_w1 rc_w1
PM0214
17 16
rc_w1 rc_w1
2 1 0
rc_w1 rc_w1