Table of Contents
Advertisement
Model 4200-SCS Reference Manual
Figure 12-6
Pulse IV schematic diagram
Figure 12-7
Waveforms at select points in
At the start of the test, the drain of the device under test (DUT) is biased with SMU2 and is waiting
for a gate pulse to turn on the transistor and cause drain current, Id, to flow.
A.
B.
4200-901-01 Rev. S / May 2017
Gate Voltage Pulse: This waveform is the output from Channel 1 of the PG2 pulse generator
card. Its amplitude is about the same as that seen by the DUT gate (C), except for some
small cable losses. Note that there is no DC offset on this waveform, as any DC voltage
would cause excessive power to be dissipated in the power divider.
Gate voltage pulse measured by the oscilloscope (scope card channel 1): This is the portion
of the pulse that is transmitted through the power divider. Because of the divider and the
50 Ω input impedance of the scope, the amplitude of the pulse is reduced 33%, plus any
additional cable losses. The PulseIV calibration accounts for this loss caused by the power
divider and cabling. The power splitter splits the power in half (3dB), which means that the
Return to
Section 12: Pulse Projects for Models 4200-PIV-A and 4200-PIV-Q
Figure 12-6
Section Topics
12-7
Advertisement
Chapters
Table of Contents
