Motorola DSP56309 User Manual page 194

first time slot in the frame. When the RFS bit is cleared and a word is received, it
indicates (only in Network mode) that the frame sync did not occur during reception of
that word. RFS is valid only if the receiver is enabled (i.e., the RE bit is set).
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears RFS.
Note: In normal mode, RFS is always read as 1 when reading data because there is
only one time slot per frame, the frame sync time slot.
7.4.3.5 SSISR Transmitter Underrun Error Flag (TUE) Bit 4
The TUE bit is set when at least one of the enabled serial transmit shift registers is empty
(no new data to be transmitted) and a transmit time slot occurs. When a transmit
underrun error occurs, the previous data (which is still present in the TX registers that
were not written) is retransmitted. In normal mode, there is only one transmit time slot
per frame. In network mode, there can be up to thirty-two transmit time slots per frame.
If the TEIE bit is set, a DSP transmit underrun error interrupt request is issued when the
TUE bit is set.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears TUE. TUE can also be cleared by first reading the SSISR with the TUE
bit set, then writing to all the enabled transmit data registers or to the TSR.
7.4.3.6 SSISR Receiver Overrun Error Flag (ROE) Bit 5
The ROE bit is set when the serial receive shift register is filled and ready to transfer to
the receive data register (RX), but RX is already full (i.e., the RDF bit is set). If the REIE
bit is set, a DSP receiver overrun error interrupt request is issued when the ROE bit is set.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears ROE. ROE can also be cleared by reading the SSISR with the ROE bit
set and then reading the RX.
7.4.3.7 ESSI Transmit Data Register Empty (TDE) Bit 6
The TDE bit is set when the contents of the transmit data register of every enabled
transmitter are transferred to the transmit shift register. It is also set for a TSR disabled
time slot period in network mode (as if data were being transmitted after the TSR was
written). When set, the TDE bit indicates that data should be written to all the TX
registers of the enabled transmitters or to the TSR. The TDE bit is cleared when the
DSP56309 writes to all the transmit data registers of the enabled transmitters or when the
DSP writes to the TSR to disable transmission of the next time slot. If the TIE bit is set, a
DSP transmit data interrupt request is issued when TDE is set. A hardware RESET
signal, software RESET instruction, ESSI individual reset, or STOP instruction clears the
TDE bit.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
DSP56309UM/D
ESSI Programming Model
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