Motorola DSP56309 User Manual page 266

The duty cycle of the TIO signal is determined by the value in the TCPR. When the value
in the TLR is incremented to a value equal to the value in the TCPR, the TIO signal is
toggled. The duty cycle is equal to ($FFFFFF Ð TCPR) divided by ($FFFFFF - TLR + 1).
For a 50% duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1) / 2.
Note: The value in TCPR must be greater than the value in TLR.
9.4.4 Watchdog Modes
The following watchdog timer modes are provided:
¥ Watchdog pulse
¥ Watchdog toggle
9.4.4.1 Watchdog Pulse (Mode 9)
Bit Settings
TC3 TC2 TC1
1 0 0
In this mode, the timer generates an external signal at a preset rate. The signal period is
equal to the period of one timer clock.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TCPR. The counter is loaded with the TLR value on the first
timer clock received from either the DSP56309 internal clock divided by two (CLK/2) or
the prescaler clock output. Each subsequent timer clock increments the counter.
When the counter matches the value of the TCPR, the TCF bit in the TCSR is set and a
compare interrupt is generated if the TCIE bit is also set.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and
the count is resumed. If the TRM bit is cleared, the counter continues to be incremented
on each subsequent timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared).
MOTOROLA
TC0 Mode Name
1 9 Pulse
DSP56309UM/D
Timer Operational Modes
Mode Characteristics
Function
Watchdog
Triple Timer Module
TIO Clock
Output Internal
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