Motorola DSP56309 User Manual page 198

7.4.4 ESSI Receive Shift Register
The 24-bit receive shift register (in Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32) receives the incoming data from the serial receive data signal. Data is shifted
in by the selected (internal/external) bit clock when the associated frame sync I/O is
asserted. It is assumed that data is received MSB first if SHFD is cleared and LSB first if
SHFD is set. Data is transferred to the ESSI receive data register after 8, 12, 16, 24, or 32
serial clock cycles are counted, depending on the word-length control bits in the CRA.
7.4.5 ESSI Receive Data Register (RX)
The receive data register (RX) is a 24-bit, read-only register that accepts data from the
receive shift register as it becomes full; see Figure 7-16 on page 7-31 and Figure 7-17 on
page 7-32. The data read is aligned according to the value of the ALC bit. When the ALC
bit is cleared, the MSB is bit 23 and the least significant byte is unused. When the ALC bit
is set, the MSB is bit 15 and the most significant byte is unused. Unused bits are read as
0s. If the associated interrupt is enabled, the DSP is interrupted whenever the RX register
becomes full.
7.4.6 ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted; see
Figure 7-16 on page 7-31 and Figure 7-17 on page 7-32. Data is shifted out to the serial
transmit data signals by the selected (internal/external) bit clock when the associated
frame sync I/O is asserted. The word-length control bits in the CRA determine the
number of bits that must be shifted out before the shift registers are considered empty
and can be written to again. Depending on the setting of the CRA, the number of bits to
be shifted out can be 8, 12, 16, 24, or 32 bits.
The data transmitted is aligned according to the value of the ALC bit. When the ALC bit
is cleared, the MSB is bit 23 and the least significant byte is unused. When ALC is set, the
MSB is bit 15 and the most significant byte is unused. Unused bits are read as 0s. Data is
shifted out of these registers MSB first if the SHFD bit is cleared and LSB first if the
SHFD bit is set.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
DSP56309UM/D
ESSI Programming Model
7-33