Figure 6-8 Dual Strobe Bus - Motorola DSP56309 User Manual

Host Interface (HI08)
HI08 DSP Side ProgrammerÕs Model
Data
HWR
Data
HRD
In dual strobe bus, there are separate HRD and HWR signals that specify the access as being
a read or write access, respectively.
6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13
If the HCSP bit is cleared, the host chip select (HCS) signal is configured as an active low
input and the HI08 is selected when the HCS signal is low. If the HCSP signal is set, HCS
is configured as an active high input, and the HI08 is selected when the HCS signal is
high.
6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14
The HRP bit controls the polarity of the host request signals. In the single-host request
mode (HDRQ is cleared in the ICR), if HRP is cleared, and host requests are enabled
(HREN is set and HEN is set), the HREQ signal is an active low output. If HRP is set and
host requests are enabled, the HREQ signal is an active high output.
In the double-host request mode (HDRQ is set in the ICR), if HRP is cleared, and host
requests are enabled (HREN is set and HEN is set), the HTRQ and HRRQ signals are
active low outputs. If HRP is set, and host requests are enabled, the HTRQ and HRRQ
signals are active high outputs.
6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15
If the HAP bit is cleared, the host acknowledge (HACK) signal is configured as an active
low input. The HI08 drives the contents of the IVR onto the host bus when the HACK
signal is low. If the HAP bit is set, the HACK signal is configured as an active high input.
The HI08 outputs the contents of the IVR when the HACK signal is high.
6-16
Write Cycle
Read Cycle

Figure 6-8 Dual Strobe Bus

DSP56309UM/D
Write Data In
Read Data Out
AA0662
MOTOROLA