Motorola DSP56309 User Manual page 181

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
Bit OF0 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.1.2 CRB Serial Output Flag 1 (OF1) Bit 1
When the ESSI is in synchronous mode and transmitter 2 is disabled (TE2 = 0), the SC1
signal is configured as ESSI flag 1. If the serial control direction bit (SCD1) is set, the SC1
signal is an output. Data present in bit OF1 is written to SC1 at the beginning of the
frame in normal mode or at the beginning of the next time slot in network mode.
Bit OF1 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.2 CRB Serial Control Direction 0 (SCD0) Bit 2
In synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0), or in
asynchronous mode (SYN = 0), SCD0 controls the direction of the SC0 I/O signal. When
SCD0 is set, SC0 is an output; when SCD0 is cleared, SC0 is an input.
When TE1 is set, the value of SCD0 is ignored, and the SC0 signal is always an output.
Bit SCD0 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.3 CRB Serial Control Direction 1 (SCD1) Bit 3
In synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0), or in
asynchronous mode (SYN = 0), SCD1 controls the direction of the SC1 I/O signal. When
SCD1 is set, SC1 is an output; when SCD1 is cleared, SC1 is an input.
When TE2 is set, the value of SCD1 is ignored, and the SC1 signal is always an output.
Bit SCD1 is cleared by a hardware RESET signal or by a software RESET instruction.
7.4.2.4 CRB Serial Control Direction 2 (SCD2) Bit 4
SCD2 controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output;
when SCD2 is cleared, SC2 is an input. SCD2 is cleared by a hardware RESET signal or
by a software RESET instruction.
7.4.2.5 CRB Clock Source Direction (SCKD) Bit 5
SCKD selects the source of the clock signal. If SCKD is set and the ESSI is in synchronous
mode, the internal clock is the source of the clock signal used for all the transmit shift
registers and the receive shift register. If SCKD is set and the ESSI is in asynchronous
mode, the internal clock source becomes the bit clock for the transmit shift register and
word length divider. The internal clock is output on the SCK signal.
When SCKD is cleared, the external clock source is selected. The internal clock generator
is disconnected from the SCK signal, and an external clock source can drive this signal.
Either a hardware RESET signal or a software RESET instruction clears SCKD.
7-16 DSP56309UM/D MOTOROLA