Motorola DSP56309 User Manual page 20

Figure 1-1 DSP56309 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . 2-4
Figure 3-1 Default Settings (0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Figure 3-2 Instruction Cache Enabled (0, 0, 1) . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-3 Switched Program RAM (0, 1, 0). . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1)3-13
Figure 3-5 16-bit Space with Default RAM (1, 0, 0) . . . . . . . . . . . . . . . . . . 3-14
Figure 3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1) . . . . . . . 3-15
Figure 3-7 16-bit Space with Switched Program RAM (1, 1, 0) . . . . . . . . . 3-16
Figure 3-8 16-bit Space, Switched Program RAM, Instruction Cache . . . . 3-17
Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . 4-13
Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . 4-13
Figure 4-3 DSP56309 Operating Mode Register (OMR) . . . . . . . . . . . . . . 4-17
Figure 4-4 PLL Control (PCTL) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Figure 4-5 Identification Register Configuration (Revision 0) . . . . . . . . . . . 4-19
Figure 4-6 Address Attribute Registers (AAR0ÐAAR3). . . . . . . . . . . . . . . . 4-20
Figure 6-1 HI08 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2). . . . . . . . . . . . . . . . . 6-9
Figure 6-3 Host Status Register (HSR) (X:$FFFFC3) . . . . . . . . . . . . . . . . 6-11
MOTOROLA
LIST OF FIGURES
DSP56309UM/D xvii