Motorola DSP56309 User Manual page 193

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.3.1 SSISR Serial Input Flag 0 (IF0) Bit 0
The IF0 bit is enabled only when SC0 is an input flag and synchronous mode is selected
(i.e., when the SYN bit is set, and the TE1 and SCD0 bits are cleared).
The ESSI latches data present on the SC0 signal during reception of the first received bit
after the frame sync is detected. The IF0 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register.
If it is not enabled, the IF0 bit is cleared.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the IF0 bit.
7.4.3.2 SSISR Serial Input Flag 1 (IF1) Bit 1
The IF1 bit is enabled only when SC1 is an input flag and synchronous mode is selected,
the SYN bit is set, and the TE2 and SCD1 bits are cleared.
The ESSI latches data present on the SC1 signal during reception of the first received bit
after the frame sync is detected. The IF1 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register.
If it is not enabled, the IF1 bit is cleared.
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears the IF1 bit.
7.4.3.3 SSISR Transmit Frame Sync Flag (TFS) Bit 2
When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS
is set at the start of the first time slot in the frame and cleared during all other time slots.
If the transmitter is enabled, data written to a transmit data register during the time slot
when TFS is set is transmitted (in network mode) during the second time slot in the
frame. TFS is useful in network mode to identify the start of a frame. TFS is valid only if
at least one transmitter is enabled (TE0, TE1 or TE2 are set).
A hardware RESET signal, software RESET instruction, ESSI individual reset, or STOP
instruction clears TFS.
Note: In normal mode, TFS is always read as 1 when transmitting data because there
is only one time slot per frame, the Ôframe syncÕ time slot.
7.4.3.4 SSISR Receive Frame Sync Flag (RFS) Bit 3
When set, the RFS bit indicates that a receive frame sync occurred during the reception
of a word in the serial receive data register. This means that the data word is from the
7-28 DSP56309UM/D MOTOROLA