Figure 6-12 Interface Control Register; Table 6-7 Host Side Register Map - Motorola DSP56309 User Manual

Host Interface (HI08)
HI08-External Host ProgrammerÕs Model
Host
Address
0
1
2
3
4
5
6
7
6.6.1 Interface Control Register (ICR)
The ICR is an 8-bit, read/write control register by which the host processor controls the
HI08 interrupts and flags. It is illustrated in Figure 6-12. The DSP core cannot access the
ICR. The ICR is a read/write register, which allows the use of bit manipulation
instructions on control register bits. The control bits are described in the following
paragraphs.
6-22

Table 6-7 Host Side Register Map

Big Endian
HLEND = 0
ICR
CVR
ISR
IVR
00000000
RXH/TXH
RXM/TXM
RXL/TXL
Host Data Bus
H0 - H7
7 6 5
INIT HLEND HF1
ÑReserved bit. Read as 0. Should be written with 0, for future compatibility.

Figure 6-12 Interface Control Register

DSP56309UM/D
Little Endian
HLEND = 1
ICR
CVR
ISR
IVR
00000000
RXL/TXL
RXM/TXM
RXH/TXH
Host Data Bus
H0 - H7
4 3 2 1
HF0 HDRQ TREQ
Interface Control
Command Vector
Interface Status
Interrupt Vector
Unused
Receive/Transmit
Bytes
0
RREQ
AA0668
MOTOROLA