Motorola DSP56309 User Manual page 343

24-bit digital signal processor
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Equates
;
DMA Status Register
M_DTD
EQU
$3F
M_DTD0
EQU
0
M_DTD1
EQU
1
M_DTD2
EQU
2
M_DTD3
EQU
3
M_DTD4
EQU
4
M_DTD5
EQU
5
M_DACT
EQU
8
M_DCH
EQU
$E00
;(DCH0DCH2)
M_DCH0
EQU
9
M_DCH1
EQU
10
M_DCH2
EQU
11
B.8
PHASE-LOCKED LOOP (PLL) EQUATES
;---------------------------------------------------------------
;Phase Locked Loop (PLL) equates
;---------------------------------------------------------------
;
Register Addresses Of PLL
M_PCTL
EQU
$FFFFFD
;
PLL Control Register
M_MF
EQU
$FFF
M_DF
EQU
$7000
M_XTLR
EQU
15
M_XTLD
EQU
16
M_PSTP
EQU
17
M_PEN
EQU
18
M_PCOD
EQU
19
M_PD
EQU
$F00000
B-12
;Channel Transfer Done Status MASK
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; DMA Active State
; DMA Active Channel Mask
; DMA Active Channel 0
; DMA Active Channel 1
; DMA Active Channel 2
; PLL Control Register
; Multiplication Factor Bit Mask (MF0-MF11)
; Division Factor Bit Mask (DF0-DF2)
; XTAL Range select bit
; XTAL Disable Bit
; STOP Processing State Bit
; PLL Enable Bit
; PLL Clock Output Disable Bit
; PreDivider Factor Bit Mask (PD0-PD3)
DSP56309UM/D
MOTOROLA

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