Motorola DSP56309 User Manual page 422

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TE bit 8-10 9-9
TE0 bit 7-24
TE1 bit 7-23
TE2 bit 7-22
TEIE bit 7-27
Test Access Port (TAP) 1-11
Test Clock Input pin (TCK) 11-5
Test Data Input pin (TDI) 11-5
Test Mode Select Input pin (TMS) 11-5
Test Reset Input pin (TRST) 11-5
TFS bit 7-28
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TIE bit 7-26 8-12
Time Slot Register (TSR) 7-34
timer
special cases 9-27
Timer (GPIO) 5-4
timer 0 signal (TIO0) 2-34
timer 1 signal (TIO1) 2-34
timer 2 signal (TIO2) 2-35
Timer Control bits (TC0ÐTC3) 9-10
Timer Control/Status Register (TCSR) 9-9
Timer Count Register (TCR) 9-16
Timer Enable bit (TE) 9-9
Timer Interrupt Enable bit (TMIE) 8-12
Timer Interrupt Rate bit (STIR) 8-12
timer mode
mode 0ÑGPIO 9-17
mode 1Ñtimer pulse 9-18
mode 2Ñtimer toggle 9-19
mode 3Ñtimer event counter 9-20
mode 4Ñmeasurement input width 9-21
mode 5Ñmeasurement input period 9-22
mode 6Ñmeasurement capture 9-23
mode 7Ñpulse width modulation 9-24
mode 8Ñreserved 9-25
mode 9Ñwatchdog pulse 9-25
mode 10Ñmeasurement toggle 9-26
modes 11Ð15Ñreserved 9-27
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Timer module 1-17 2-34
architecture 9-3
programming model 9-5
timer block diagram 9-4
Timer Prescaler Count Register (TPCR) 9-8
Timer Prescaler Load Register (TPLR) 9-7
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Timers 2-3 2-4
TLIE bit 7-26
TME bit 10-8
TMIE bit 8-12
TMS pin 11-5
TMS signal 2-36
TO bit 10-9
MOTOROLA
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11-3
DSP56309UM/D
TOIE 9-9
TPCR register 9-8
bits 0-20ÑPrescaler Counter Value bits
(PC0-PC20) 9-9
bit 21-23Ñreserved bits 9-9
reserved bitsÑbits 21-23 9-9
TPLR register 9-7
bits 0-20ÑPrescaler Load Value bits
(PL0-PL20) 9-7
bits 21-22ÑPrescaler Source bits
(PL0-PL20) 9-7
bit 23Ñreserved bit 9-8
reserved bitÑbit 23 9-8
Trace buffer 10-21
Trace mode
enabling 10-18
in OnCE module 10-15
Trace Mode Enable bit (TME) 10-8
Trace Occurrence bit (TO) 10-9
transfer acknowledge signal 2-11
Transmit 0 Enable bit (TE0) 7-24
Transmit 1 Enable bit (TE1) 7-23
Transmit 2 Enable bit (TE2) 7-22
Transmit Byte Registers (TXH, TXM, TXL) 6-29
Transmit Clock Source bit (TCM) 8-18
Transmit Data Register Empty bit (TDE) 7-29
Transmit Data Register Empty bit (TDRE) 8-13
Transmit Data Register Empty bit (TXDE) 6-27
Transmit Data signal (TXD) 8-4
Transmit Exception Interrupt Enable bit
(TEIE) 7-27
Transmit Frame Sync Flag bit (TFS) 7-28
transmit host request signal (HTRQ/HTRQ) 2-22
Transmit Interrupt Enable bit (TIE) 7-26
Transmit Last Slot Interrupt Enable bit (TLIE) 7-26
Transmit Request Enable bit (TREQ) 6-23
Transmit Shift Registers 7-33
Transmit Slot Mask Registers (TSMA, TSMB) 7-34
Transmitter Empty bit (TRNE) 8-13
Transmitter Enable bit (TE) 8-10
Transmitter Ready bit (TRDY) 6-27
Transmitter Underrun Error Flag bit (TUE) 7-29
TRDY bit 6-27
TREQ bit 6-23
triple timer module 1-17
TRNE bit 8-13
TRST pin 11-5
TSMA, TSMB registers 7-34
TSR register 7-34
TUE bit 7-29
TX2, TX1, TX0 registers 7-34
T
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8-12
I-13