Motorola DSP56309 User Manual page 414

Receive Byte Registers (RXH, RXM,
RXL) 6-28
Transmit Byte Registers (TXH, TXM,
TXL) 6-29
host side registers after reset 6-30
Host Status Register (HSR) 6-11
host to DSP
data word 6-3
handshaking protocols 6-4
instructions 6-4
mapping 6-3
transfer modes 6-3
Host Transmit Data Register (HTX) 6-9
polling 6-31
registers 6-7
servicing interrupts 6-32
HI-Z instruction 11-10
HLEND bit 6-24
HMUX bit 6-15
Host Acknowledge Enable bit (HAEN) 6-14
Host Acknowledge Polarity bit (HAP) 6-16
host acknowledge signal (HACK/HACK 2-23
host address 10 signal (HA10) 2-21
host address 8 signal (HA8) 2-19
host address 9 signal (HA9) 2-19
host address input 0 signal (HA0) 2-18
host address input 1 signal (HA1) 2-19
host address input 2 signal (HA2) 2-19
Host Address Line 8 Enable bit (HA8EN) 6-13
Host Address Line 9 Enable bit (HA9EN) 6-13
host address signal HAD0ÐHAD7) 2-18
Host Address Strobe Polarity bit (HASP) 6-15
host address strobe signal (HAS/HAS) signal 2-18
Host Base Address Register (HBAR) 6-12
Host Chip Select Enable bit (HCSEN) 6-13
Host Chip Select Polarity bit (HCSP) 6-16
host chip select signal (HCS) 2-21
Host Command Interrupt Enable bit (HCIE) 6-10
Host Command Pending bit (HCP) 6-11
Host Control Register (HCR) 6-9
Host Data Direction Register (HDDR) 6-17
Host Data Register (HDR) 6-17
host data signal (H0ÐH7) 2-18
Host Data Strobe Polarity bit (HDSP) 6-14
host data strobe signal (HDS/HDS) 2-20
Host Dual Data Strobe bit (HDDS) 6-15
Host Enable bit (HEN) 6-14
Host Flag 0 and 1 bits (HF0, HF1) 6-11
Host Flag 0 bit (HF0) 6-24
Host Flag 1 bit (HF1) 6-24
Host Flag 2 and 3 bits (HF2, HF3) 6-10
MOTOROLA
Host Flag 2 bit (HF2) 6-27
Host Flag 3 bit (HF3) 6-27
Host GPIO Port Enable bit (HGEN) 6-13
Host Interface 1-16
Host Little Endian bit (HLEND) 6-24
Host Multiplexed Bus bit (HMUX) 6-15
host port
Host Port Control Register (HPCR) 6-12
host read data signal (HRD/HRD) signal 2-20
host read/write signal (HRW) 2-20
Host Receive Data Full bit (HRDF) 6-11
Host Receive Data Register (HRX) 6-8
Host Receive Interrupt Enable bit (HRIE) 6-10
Host Request
Host Request Enable bit (HREN) 6-14
Host Request Open Drain bit (HROD) 6-14
Host Request Polarity bit (HRP) 6-16
host request signal (HREQ/HREQ 2-22
Host Status Register (HSR) 6-11
Host Transmit Data Empty bit (HTDE) 6-11
Host Transmit Data Register (HTX) 6-9
Host Transmit Interrupt Enable bit (HTIE) 6-10
Host Vector bits (HV0ÐHV6) 6-25
host write data signal (HWR/HWR) 2-20
HPCR register 6-12
,
6-10
DSP56309UM/D
, ,
2-3 2-4
6-3
configuration 2-17
usage considerations 2-16
Double 2-4
Single 2-4
bit 0ÑHost GPIO Port Enable bit (HGEN) 6-13
bit 1ÑHost Address Line 8 bit (HA8EN) 6-13
bit 2ÑHost Address Line 9 bit (HA9EN) 6-13
bit 3ÑHost Chip Select Enable bit
(HCSEN) 6-13
bit 4ÑHost Request Enable bit (HREN) 6-14
bit 5ÑHost Acknowledge Enable bit
(HAEN) 6-14
bit 6ÑHost Enable bit (HEN) 6-14
bit 7Ñreserved bit 6-14
bit 8ÑHost Request Open Drain bit
(HROD) 6-14
bit 9ÑHost Data Strobe Polarity bit
(HDSP) 6-14
bit 10ÑHost Address Strobe Polarity bit
(HASP) 6-15
bit 11ÑHost Multiplexed Bus bit (HMUX) 6-15
bit 12ÑHost Dual Data Strobe bit (HDDS) 6-15
bit 13ÑHost Chip Select Polarity bit
(HCSP) 6-16
bit 14ÑHost Request Polarity bit (HRP) 6-16
H
, , , , ,
2-16 2-18 2-19 2-21
I-5