Motorola DSP56309 User Manual page 191

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.2.17 CRB ESSI Receive Enable (RE) Bit 17
When the RE bit is set, the receive portion of the ESSI is enabled. When this bit is cleared,
the receiver is disabled by inhibiting data transfer into RX. If data is being received while
this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI
receive data register.
RE must be set in both the normal and on-demand modes for the ESSI to receive data. In
network mode, clearing RE and setting it again disables the receiver after reception of
the current data word. The receiver remains disabled until the beginning of the next data
frame.
RE is cleared by either a hardware RESET signal or a software RESET instruction.
Note: The setting of the RE bit does not affect the generation of a frame sync.
7.4.2.18 CRB ESSI Transmit Interrupt Enable (TIE) Bit 18
Setting the TIE bit enables a DSP transmit interrupt, which is generated when both the
TIE and the TDE bits in the ESSI status register are set. When TIE is cleared, the transmit
interrupt is disabled. The use of the transmit interrupt is described in Section 7.5.3.
Writing data to the data registers of the enabled transmitters or to the TSR clears TDE
and also clears the interrupt. Transmit interrupts with exception conditions have higher
priority than normal transmit data interrupts. If the transmitter underrun error (TUE) bit
is set, signaling that an exception has occurred, and the TEIE bit is set, the ESSI requests
an SSI transmit data with exception interrupt from the interrupt controller.
TIE is cleared by either a hardware RESET signal or a software RESET instruction.
7.4.2.19 CRB ESSI Receive Interrupt Enable (RIE) Bit 19
Setting the RIE enables a DSP receive data interrupt, which is generated when both the
RIE and receive data register full (RDF) bit in the SSISR are set. When RIE is cleared, this
interrupt is disabled. The use of the receive interrupt is described in Section 7.5.3.
Reading the receive data register clears RDF and the pending interrupt. Receive
interrupts with exception have higher priority than normal receive data interrupts. If the
receiver overrun error (ROE) bit is set, signaling that an exception has occurred, and the
REIE bit is set, the ESSI requests an SSI receive data with exception interrupt from the
interrupt controller.
RIE is cleared by either a hardware RESET signal or a software RESET instruction.
7.4.2.20 Transmit Last Slot Interrupt Enable (TLIE) Bit 20
Setting the TLIE bit enables an interrupt at the beginning of the last slot of a frame when
the ESSI is in network mode. When TLIE is set, the DSP is interrupted at the start of the
last slot in a frame regardless of the transmit mask register setting. When TLIE is cleared,
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