Motorola DSP56309 User Manual page 208

Enhanced Synchronous Serial Interface (ESSI)
GPIO Signals and Registers
The SC[1:0] flags are available in synchronous mode only. Each flag can be separately
programmed.
Flag SC0 is enabled when transmitter 1 is disabled (TE1 = 0). The flagÕs direction is
selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When SCD0 is
cleared, SC0 is configured as input.
Similarly, the SC1 flag is enabled when transmitter 2 is disabled (TE2 = 0) and the SC1
signal is not configured as transmitter drive enable (Bit SSC1 = 0). SC1Õs direction is
selected by the SCD1 bit. When SCD1 is set, SC1 is an output flag. When SCD1 is cleared,
SC1 is an input flag.
When programmed as input flags, the value of the SC[1:0] bits are latched at the same
time as the first bit of the receive data word is sampled. Once the input has been latched,
the signal on the input flag signal (SC0 and SC1) can change without affecting the input
flag. The value of SC[1:0] does not change until the first bit of the next data word is
received. When the received data word is latched by RX, the latched values of SC[1:0] are
latched by the respective SSISR IF[1:0] bits and can be read by software.
When programed as output flags, the value of the SC[1:0] bits is taken from the value of
the OF[1:0] bits. The value of the OF[1:0] bits is latched when the contents of TX are
transferred to the transmit shift register. The value on SC[1:0] is stable from the time the
first bit of the transmit data word is transmitted until the first bit of the next transmit
data word is transmitted. The OF[1:0] values can be set directly by software. This allows
the DSP56309 to control data transmission by indirectly controlling the value of the
SC[1:0] flags.
7.6 GPIO SIGNALS AND REGISTERS
The GPIO functionality of an ESSI port (C, D) is controlled by three registers: port
control register (PCRC, PCRD), port direction register (PRRC, PRRD) and port data
register (PDRC, PDRD).
7.6.1 Port Control Register (PCR)
The read/write, 24-bit PCR controls the functionality of the ESSI GPIO signals. Each of
PC[5:0] bits controls the functionality of the corresponding port signal. When a PC[i] bit
is set, the corresponding port signal is configured as a ESSI signal. When a PC[i] bit is
cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware
MOTOROLA DSP56309UM/D 7-43