Motorola DSP56309 User Manual page 412

bus interface unit B-13
direct memory access B-10
DMA B-10
enhanced serial communication interface B-5
ESSI B-5
exception processing B-7
HI08 B-3
host interface B-3
i/o port programming B-3
interrupt B-15
phase locked loop B-12
PLL B-12
SCI B-4
serial communication interface B-4
timer module B-9
ESSI 2-4
after reset 7-36
asynchronous operating mode 7-40
frame sync length 7-41
frame sync polarity 7-42
frame sync selection 7-41
frame sync word length 7-41
GPIO functionality 7-43
initialization 7-36
interrupts 7-37
Network mode 7-40
Normal mode 7-40
operating mode 7-36
operating modes 7-40
Port Control Register (PCR) 7-43
Port Data Register (PDR) 7-45
Port Direction Register (PRR) 7-44
programming model 7-8
synchronous operating mode 7-40
ESSI Control Register A (CRA) 7-11
ESSI Mode Select bit (MOD) 7-20
ESSI Receive Data Register (RX) 7-33
ESSI Receive Enable bit (RE) 7-26
ESSI Receive Exception Interrupt Enable bit
(REIE) 7-27
ESSI Receive Interrupt Enable bit (RIE) 7-26
ESSI Receive Last Slot Interrupt Enable bit
(RLIE) 7-27
ESSI Receive Shift Register 7-33
ESSI Receive Slot Mask Registers (RSMA,
RSMB) 7-35
ESSI Status Register (SSISR) 7-27
ESSI Time Slot Register (TSR) 7-34
ESSI Transmit 0 Enable bit (TE0) 7-24
ESSI Transmit 1 Enable bit (TE1) 7-23
ESSI Transmit 2 Enable bit (TE2) 7-22
MOTOROLA
ESSI Transmit Data registers (TX2, TX1, TX0) 7-34
ESSI Transmit Exception Interrupt Enable bit
(TEIE) 7-27
ESSI Transmit Interrupt Enable bit (TIE) 7-26
ESSI Transmit Last Slot Interrupt Enable bit
(TLIE) 7-26
ESSI Transmit Shift Registers 7-33
ESSI Transmit Slot Mask Registers (TSMA,
TSMB) 7-34
ESSI0 2-24
ESSI0 (GPIO) 5-3
ESSI1 2-28
ESSI1 (GPIO) 5-4
EX bit 10-5
exception processing equates B-7
Exit Command bit (EX) 10-5
expanded mode 4-6
EXTAL 2-7
EXTAL signal 2-7
external address bus 2-9
external bus control 2-9
external clock/crystal input 2-7
external data bus 2-9
external interrupt request A signal 2-14
external interrupt request B signal 2-15
external interrupt request C signal 2-15
external interrupt request D signal 2-16
external memory expansion port 2-9
EXTEST instruction 11-8
F
FE bit 8-15
Frame Rate Divider Control bits (DC4ÐDC0) 7-12
Frame Sync Length bits (FSL1ÐFSL0) 7-17
Frame Sync Polarity bit (FSP) 7-17
Frame Sync Relative Timing bit (FSR) 7-17
frame sync selection
ESSI 7-41
Framing Error Flag bit (FE) 8-15
frequency
operation 1-7
FSL1ÐFSL0 bits 7-17
FSP bit 7-17
FSR bit 7-17
functional groups 2-4
G
general purpose input/output (GPIO) 2-34
Global Data Bus 1-13
DSP56309UM/D
, ,
2-11 2-12
F
I-3