Motorola DSP56309 User Manual page 256

9.3.4.12 Timer Compare Flag (TCF) Bit 21
The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and
watchdog modes, the TCF bit is set when (N Ð M + 1) events have been counted. (N is the
value in the compare register and M is the TLR value.) In measurement modes, the TCF
bit is set when the measurement is completed.
Writing a 1 into the TCF bit clears this bit. Writing a 0 into the TCF bit has no effect. The
bit is also cleared when the timer compare interrupt is serviced.
The TCF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
Note: The TOF and TCF bits are cleared by writing a 1 to the specific bit. In order to
insure that only the desired bit is cleared, do not use the BSET command. The
proper way to clear these bits is to write (using a MOVEP instruction) a 1 to
the flag to be cleared and a 0 to the other flag.
9.3.4.13 TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23
These reserved bits are read as 0 and should be written with 0 for future compatibility.
9.3.5 Timer Load Register (TLR)
The TLR is a 24-bit, write-only register. In all modes, the counter is preloaded with the
TLR value after the TE bit in the TCSR is set and a first event occurs.
¥ In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter
is reloaded each time after it has reached the value contained by the timer
compare register (TCPR) and the new event occurs.
¥ In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the
TCSR is set, the counter is reloaded with the value in the TLR on each appropriate
edge of the input signal.
¥ In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each
time after it has overflowed and the new event occurs.
¥ In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each
time after it has reached the value contained by the TCPR and the new event
occurs. In this mode, the counter is also reloaded whenever the TLR is written
with a new value while the TE bit in the TCSR is set.
¥ In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates
as a free-running counter.
MOTOROLA
Triple Timer Module Programming Model
DSP56309UM/D
Triple Timer Module
9-15