Motorola DSP56309 User Manual page 204

1. Configure interrupt service routine (ISR)
a. Load vector base address register.
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt or
jump/branch to subroutine (long interrupt).
2. Configure interrupt trigger/preload transmit data
a. Enable and prioritize overall peripheral interrupt functionality.
b. Enable peripheral and associated signals.
c. Write data to all enabled transmit registers.
d. Enable peripheral interrupt-generating function.
e. Enable specific peripheral interrupt.
f. Unmask interrupts at global level.
Notes: 1. The example material to the right of the steps above shows register settings
for configuring an ESSI0 transmit interrupt using transmitter 0.
2. The order of the steps is optional except that the interrupt trigger
configuration must not be completed until the ISR configuration has been
completed. Since 2d can cause an immediate transmit without generating
an interrupt, perform the transmit data preload in 2c before 2d to insure
valid data is sent in the first transmission.
3. After the first transmit, subsequent transmit values are typically loaded
into TXnn by the ISR (one value per register per interrupt). Therefore, if N
items are to be sent from a particular TXnn, the ISR will need to load the
transmit register (N Ð 1) times.
4. Steps d and e can be performed using a single instruction.
5. If an interrupt trigger event occurs at a time when not all interrupt trigger
configuration steps have been performed, the event is ignored forever (the
event is not queued in this case).
6. If interrupts derived from the core or other peripherals need to be enabled
at the same time as ESSI interrupts, step f should be done last.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
DSP56309UM/D
Operating Modes
VBA (b23:8)
p:I_SI0TD
IPRP (S0L1:0)
PCRC (PC5:0)
TX00
CRB (TE0)
CRB0 (TIE)
SR (I1:0)
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