Motorola DSP56309 User Manual page 156

low bytes, respectively, of the HTX register and are selected by the external host address
inputs (HA[2:0]) during a host processor read operation.
The memory address of the receive byte registers is set by the HLEND bit in the ICR. If
the HLEND bit is set, the RXH is located at address $7, RXM at $6, and RXL at $5. If the
HLEND bit is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7.
When data is written to the receive byte register at host address $7, the receive data
register full (RXDF) bit is set. The host processor can program the RREQ bit to assert the
external HREQ signal when RXDF is set. This indicates that the HI08 has a full word
(either 8, 16, or 24 bits) for the host processor. The host processor can program the RREQ
bit to assert the external HREQ signal when RXDF is set. Asserting the HREQ signal
informs the host processor that the receive byte registers have data to be read. When the
host reads the receive byte register at host address $7, the RXDF bit is cleared.
6.6.6 Transmit Byte Registers (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit, write-only registers.
These registers are the transmit high register (TXH), the transmit middle register (TXM),
and the transmit low register (TXL). These registers send data to the high, middle, and
low bytes, respectively, of the HRX register and are selected by the external host address
inputs, HA[2:0], during a host processor write operation.
If the HLEND bit in the ICR is set, the TXH register is located at address $7, the TXM
register at $6 and the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH
register is located at address $5, the TXM register at $6, and the TXL register at $7.
Data is written into the transmit byte registers when the transmit data register empty
(TXDE) bit is set. The host processor programs the TREQ bit to assert the external
HREQ/HTRQ signal when TXDE is set. This informs the host processor that the
transmit byte registers are empty. Writing to the data register at host address $7 clears
the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to
the HRX register when both the TXDE and the HRDF bit are cleared. This transfer
operation sets TXDE and HRDF.
Note: When data is written to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write for further details.
MOTOROLA
HI08-External Host ProgrammerÕs Model
DSP56309UM/D
Host Interface (HI08)
6-29