Motorola DSP56309 User Manual page 286

the first command. This process is the same for any newly fetched instruction, including
instructions fetched by the interrupt processing or instructions that will be aborted by
the interrupt processing.
Note: In this case the chip completes the execution of the current instruction and
stops after the newly fetched instruction enters the instruction latch.
10.7.3 Executing the JTAG DEBUG_REQUEST Instruction
Executing the JTAG instruction DEBUG_REQUEST asserts an internal debug request
signal. Consequently, the chip finishes the execution of the current instruction and stops
after the newly fetched instruction enters the instruction latch. After entering debug
mode, the core status bits OS1 and OS0 are set and the DE line is asserted, thus
acknowledging the external command controller that debug mode has been entered.
10.7.4 External Debug Request During Stop
Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in
the stop state (i. e., has executed a STOP instruction) causes the chip to exit the stop state
and enter debug mode. After receiving the acknowledge, the external command
controller must negate DE before sending the first command.
Note: In this case, the chip completes the execution of the STOP instruction and halts
after the next instruction enters the instruction latch.
10.7.5 External Debug Request During Wait
Executing the JTAG instruction DEBUG_REQUEST (or asserting DE) while the chip is in
the wait state (i. e., has executed a WAIT instruction) causes the chip to exit the wait state
and enter debug mode. After receiving the acknowledge, the external command
controller must negate DE before sending the first command.
Note: In this case, the chip completes the execution of the WAIT instruction and
halts after the next instruction enters the instruction latch.
MOTOROLA DSP56309UM/D
On-Chip Emulation Module
Methods of Entering Debug Mode
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