Motorola DSP56309 User Manual page 151

Host Interface (HI08)
HI08-External Host ProgrammerÕs Model
6.6.1.4 ICR Host Flag 0 (HF0) Bit 3
The HF0 bit is a general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF0, and the DSP56309 cannot change this bit. HF0 is reflected
in the HSR on the DSP side of the HI08.
6.6.1.5 ICR Host Flag 1 (HF1) Bit 4
The HF1 bit is a general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF1, and the DSP56309 cannot change this bit. HF1 is reflected
in the HSR on the DSP side of the HI08.
6.6.1.6 ICR Host Little Endian (HLEND) Bit 5
If the HLEND bit is cleared, the host can access the HI08 in big endian byte order. If set,
the host can access the HI08 in little endian byte order. If the HLEND bit is cleared the
RXH/TXH register is located at address $5, the RXM/TXM register at $6, and the
RXL/TXL register at $7. If the HLEND bit is set, the RXH/TXH register is located at
address $7, the RXM/TXM register at $6, and the RXL/TXL register at $5.
6.6.1.7 ICR Reserved Bit 6
This bit is reserved. It is read as 0 and should be written with 0.
6.6.1.8 ICR Initialize Bit (INIT) Bit 7
The host processor uses the INIT bit to force initialization of the HI08 hardware. During
initialization, the HI08 transmit and receive control bits are configured. Using the INIT
bit to initialize the HI08 hardware may or may not be necessary, depending on the
software design of the interface.
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