Servicing The Host Interface - Motorola DSP56309 User Manual

connected to the HI08 may need external pull-up/pull-down resistors until the signals
are configured for operation. The registers cleared are the HPCR, HDDR, and HDR.
Selection between GPIO and HI08 is made by clearing HPCR bits 6 through 1 for GPIO
or setting these bits for HI08 functionality. If the HI08 is in GPIO mode, the HDDR
configures each corresponding signal in the HDR as an input signal if the HDDR bit is
cleared or as an output signal if the HDDR bit is set. (See Section 6.5.7ÑHost Data
Direction Register (HDDR) on page 6-17 and Section 6.5.8ÑHost Data Register (HDR)
also on page 6-17.)
6.7

SERVICING THE HOST INTERFACE

The HI08 can be serviced by using one of the following protocols:
¥ Polling
¥ Interrupts
The host processor writes to the appropriate HI08 register to reset the control bits and
configure the HI08 for proper operation.
6.7.1 HI08 Host Processor Data Transfer
To the host processor, the HI08 looks like a contiguous block of Static RAM. To transfer
data between itself and the HI08, the host processor performs the following steps:
1. asserts the HI08 address to select the register to be read or written
2. selects the direction of the data transfer
(If it is writing, the host processor sources the data on the bus.)
3. strobes the data transfer
6.7.2 Polling
In polling mode, the HREQ/HTRQ signal is not connected to the host processor and
HACK must be deasserted to insure IVR data is not being driven on H[7:0] when other
registers are being polled. (If the HACK function is not needed, the HACK signal can be
configured as a GPIO signal, as documented in Section 6.5.6ÑHost Port Control
Register (HPCR) on page 6-12.)
MOTOROLA DSP56309UM/D
Host Interface (HI08)
Servicing the Host Interface
6-31