Motorola DSP56309 User Manual page 221

Serial Communication Interface (SCI)
SCI Programming Model
When the receiver wakes up, RWU is cleared by the wakeup hardware. The
programmer can also clear the RWU bit to wake up the receiver.
RWU can be used by the programmer to ignore messages that are for other devices on a
multidrop serial network. Wakeup on idle line (WAKE is cleared) or wakeup on address
bit (WAKE is set) must be chosen.
1. When WAKE is cleared and RWU is set, the receiver does not respond to data on
the data line until an idle line is detected.
2. When WAKE is set and RWU is set, the receiver does not respond to data on the
data line until a data frame with the address bit set is detected.
When the receiver wakes up, the RWU bit is cleared, and the first frame of data is
received. If interrupts are enabled, the CPU is interrupted and the interrupt routine
reads the message header to determine if the message is intended for this DSP.
1. If the message is for this DSP, the message is received, and RWU is set to wait for
the next message.
2. If the message is not for this DSP, the DSP immediately sets RWU. Setting RWU
causes the DSP to ignore the remainder of the message and wait for the next
message.
Either a hardware RESET signal or a software RESET instruction clears RWU. RWU is
ignored in synchronous mode.
8.3.1.6 SCR Wired-OR Mode Select (WOMS) Bit 7
When the WOMS bit is set, the SCI TXD driver is programmed to function as an
open-drain output and can be wired together with other TXD signals in an appropriate
bus configuration, such as a master-slave multidrop configuration. An external pullup
resistor is required on the bus. When the WOMS is cleared, the TXD signal uses an active
internal pullup. Either a hardware RESET signal or a software RESET instruction clears
WOMS.
8.3.1.7 SCR Receiver Enable (RE) Bit 8
When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and
data transfer from the receive shift register to the receive data register (SRX) is inhibited.
If RE is cleared while a character is being received, the reception of the character is
completed before the receiver is disabled. RE does not inhibit RDRF or receive
interrupts. Either a hardware RESET signal or a software RESET instruction clears RE.
8.3.1.8 SCR Transmitter Enable (TE) Bit 9
When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes
transmission of data in the SCI Transmit Data Shift Register, then the serial output is
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