Motorola DSP56309 User Manual page 293

On-Chip Emulation Module
OnCE Module Examples
device. The events such as select-DR, select-IR, update-DR, and shift-DR refer to
bringing the JTAG TAP in the corresponding state. For a detailed description of the
JTAG protocol, see Section 11ÑJTAG Port.
10.12.1 Checking Whether the Chip Has Entered Debug Mode
There are two methods to verify that the chip has entered debug mode:
¥ Every time the chip enters debug mode, a pulse is generated on the DE signal. A
pulse is also generated every time the chip acknowledges the execution of an
instruction while in debug mode. An external command controller can connect
the DE line to an interrupt signal in order to sense the acknowledge.
¥ An external command controller can poll the JTAG instruction shift register for
the status bits OS[1:0]. When the chip is in Debug mode, these bits are set to the
value 11.
Note: In the following paragraphs, the ACK notation denotes the operation
performed by the command controller to check whether debug mode has been
entered (either by sensing DE or by polling JTAG instruction shift register).
10.12.2 Polling the JTAG Instruction Shift Register
In order to poll the core status bits in the JTAG instruction shift register the following
sequence must be performed:
1. Select shift-IR. Passing through capture-IR loads the core status bits into the
instruction shift register.
2. Shift in ENABLE_ONCE. While shifting-in the new instruction, the captured
status information is shifted-out. Pass through update-IR.
3. Return to Run-Test/Idle.
The external command controller can analyze the information shifted out and detect
whether the chip has entered debug mode.
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