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transmit data registers (TXH:TXM:TXL on the host side) when both the hostÕs transmit
data register empty (ISR:TXDE) bit and the DSPÕs host receive data full (HSR:HRDF) bits
are cleared. The transfer operation sets both the TXDE and HRDF bits. When the HRDF
bit is set, the HRX register contains valid data. The DSP56309 sets the HRIE bit (HCR, bit
0) to cause a host receive data interrupt when HRDF is set. When the DSP56309 reads the
HRX register, the HRDF bit is cleared.
6.5.2
Host Transmit Data Register (HTX)
The HTX register handles for DSP-to-host data transfers. The DSP56309 views it as a
24-bit write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears
the DSPÕs host transfer data empty (HSR:HTDE) bit. The contents of the HTX register are
transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the
HTDE and the hostÕs receive data full (ISR:RXDF) bits are cleared. This transfer
operation sets the HTDE and RXDF bits. The DSP56309 sets the HTIE bit to cause a host
transmit data interrupt when HTDE is set. To prevent the previous data from being
overwritten, data should not be written to the HTX until the HTDE bit is set.
Note:
During data writes to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. See the DSP56300 Family Manual, Appendix B, Polling a Peripheral
Device for Write for further details.
6.5.3
Host Control Register (HCR)
The HCR is a 16-bit, read/write control register by which the DSP core controls the HI08
operating mode. Initialization values for HCR bits are documented in
Section 6.5.9ÑDSP Side Registers After Reset. Reserved bits are read as 0 and should
be written with 0 for future compatibility.
15
14
13
ÑReserved bit, read as 0, should be written with 0 for future compatibility.
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2)
MOTOROLA
12
11
10
9
DSP56309UM/D
HI08 DSP Side ProgrammerÕs Model
8
7
6
5
Host Interface (HI08)
4
3
2
1
HF3 HF2 HCIE HTIE HRIE
0
AA0658
6-9
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