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10.5
ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9
10.5.1
OnCE Memory Address Latch (OMAL). . . . . . . . . . . . . 10-11
10.5.2
OnCE Memory Limit Register 0 (OMLR0). . . . . . . . . . . 10-11
10.5.3
OnCE Memory Address Comparator 0 (OMAC0) . . . . . 10-11
10.5.4
OnCE Memory Limit Register 1 (OMLR1). . . . . . . . . . . 10-11
10.5.5
OnCE Memory Address Comparator 1 (OMAC1) . . . . . 10-11
10.5.6
OnCE Breakpoint Control Register (OBCR) . . . . . . . . . 10-12
10.5.6.1
Memory Breakpoint Select (MBS0ÐMBS1) . . . . . . . 10-12
10.5.6.2
Breakpoint 0 Read/Write Select (RW00ÐRW01) . . . 10-12
10.5.6.3
Breakpoint 0 Condition Code Select (CC00ÐCC01). 10-13
10.5.6.4
Breakpoint 1 Read/Write Select (RW10ÐRW11) . . . 10-13
10.5.6.5
Breakpoint 1 Condition Code Select (CC10ÐCC11). 10-14
10.5.6.6
Breakpoint 0 and 1 Event Select (BT0ÐBT1) . . . . . . 10-14
10.5.6.7
OnCE Memory Breakpoint Counter (OMBC) . . . . . . 10-14
10.5.6.8
Reserved Bits 12-15 . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.6
ONCE TRACE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.7
METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16
10.7.1
External Debug Request During RESET Assertion . . . 10-16
10.7.2
External Debug Request During Normal Activity . . . . . 10-16
10.7.3
Executing the JTAG DEBUG_REQUEST Instruction . . 10-17
10.7.4
External Debug Request During Stop . . . . . . . . . . . . . . 10-17
10.7.5
External Debug Request During Wait . . . . . . . . . . . . . . 10-17
10.7.6
Software Request During Normal Activity . . . . . . . . . . . 10-18
10.7.7
Enabling Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.7.8
Enabling Memory Breakpoints . . . . . . . . . . . . . . . . . . . 10-18
10.8
PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18
10.8.1
OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . 10-19
10.8.2
OnCE PIL Register (OPILR) . . . . . . . . . . . . . . . . . . . . . 10-19
10.8.3
OnCE GDB Register (OGDBR). . . . . . . . . . . . . . . . . . . 10-20
10.9
DEBUGGING RESOURCES . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.9.1
OnCE PAB Register for Fetch (OPABFR) . . . . . . . . . . 10-20
10.9.2
PAB Register for Decode (OPABDR) . . . . . . . . . . . . . . 10-20
10.9.3
OnCE PAB Register for Execute (OPABEX) . . . . . . . . 10-20
10.9.4
Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.10
SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22
10.11
TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23
xiv
DSP56309UM/D
MOTOROLA
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