Figure 9-2 Timer Module Block Diagram; Triple Timer Module Programming Model - Motorola DSP56309 User Manual

The DSP56309 views each timer as a memory-mapped peripheral with four registers
occupying four 24-bit words in the X data memory space. Either standard polled or
interrupt programming techniques can be used to service the timers. The timer
programming model is shown in Figure 9-3 on page 9-6.
GDB
24
Control/Status
Register
9
Timer Control
Logic
TIO CLK/2
9.3

TRIPLE TIMER MODULE PROGRAMMING MODEL

The programming model for the triple timer module appears in Figure 9-3 on page 9-6.
MOTOROLA
24
24
TCSR
TLR
Load
Register
2
prescaler CLK

Figure 9-2 Timer Module Block Diagram

DSP56309UM/D
Triple Timer Module Programming Model
24
TCR
Count
Register
24 24
24
Counter
Timer interrupt/
DMA request
Triple Timer Module
24
TCPR
Compare
Register
24
=
AA0676
9-5