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Functional description
IPBus (ips_rdata[7:0])
Read Access
SPI_REG_BLOCK
SPI Data Register
spidh:l_tx_reg
TX- FIFO
FIFO Ctrlr
FIFO depth = 8 bytes
SPI_CORE_SHFR
Read
shfr_tx_reg
Control
Figure 17-24. SPIH:L write side structural overview in FIFO mode
17.4.5 Data Transmission Length
The SPI can support data lengths of 8 or 16 bits. The length can be configured with the
SPIMODE bit in the SPIx_C2 register.
In 8-bit mode (SPIMODE = 0), the SPI Data Register is comprised of one byte:
SPIx_DL. The SPI Match Register is also comprised of only one byte: SPIx_ML. Reads
of SPIx_DH and SPIx_MH will return zero. Writes to SPIx_DH and SPIx_MH will be
ignored.
In 16-bit mode (SPIMODE = 1), the SPI Data Register is comprised of two bytes:
SPIx_DH and SPIx_DL. Reading either byte (SPIx_DH or SPIx_DL) latches the contents
of both bytes into a buffer where they remain latched until the other byte is read. Writing
to either byte (SPIx_DH or SPIx_DL) latches the value into a buffer. When both bytes
have been written, they are transferred as a coherent 16-bit value into the transmit data
buffer.
In 16-bit mode, the SPI Match Register is also comprised of two bytes: SPIx_MH and
SPIx_ML. There is no buffer mechanism for the reading of SPIxMH and SPIxML since
they can only be changed by writing at CPU side. Writing to either byte (SPIx_MH or
SPIx_ML) latches the value into a buffer. When both bytes have been written, they are
transferred as a coherent 16-bit value into the SPI Match Register.
Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE
bit) in master mode will abort a transmission in progress, force the SPI system into idle
state, and reset all status bits in the SPIx_S register. To initiate a transfer after writing to
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
492
Freescale Semiconductor, Inc.
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