Samsung S3C2501X User Manual page 44

S3C2501X
Group Pin Name
Ethernet CRS_0
Controller0
(18)
RX_CLK_0
RXD0[3:0]/
RXD_10M
RX_DV_0/
LINK_10M
Table 1-1. S3C2501X Signal Descriptions (Continue)
Pin Type Pad Type
1 I
1 I
4 I
1 I
phis Carrier Sense/Carrier Sense for 10M.
CRS is asserted asynchronously with
minimum delay from the detection of a non-
idle medium in MII mode. CRS_10M is
asserted when a 10-Mbit/s PHY has data to
transfer. A 10-Mbit/s transmission also uses
this signal.
phis Receive Clock/Receive Clock for 10M.
RX_CLK is a continuous clock signal. Its
frequency is 25 MHz for 100-Mbit/s operation,
and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV,
and RX_ERR are driven by the PHY off the
falling edge of RX_CLK, and sampled on the
rising edge of RX_CLK. To receive data, the
RXCLK_10 M clock comes from the 10Mbit/s
PHY.
phis Receive Data/Receive Data for 10M.
RXD is aligned on nibble boundaries. RXD[0]
corresponds to the first bit received on the
physical medium, which is the LSB of the byte
in one clock period and the fifth bit of that byte
in the next clock. RXD_10M is shared with
RXD[0] and it is a line for receiving data from
the 10-Mbit/s PHY.
phis Receive Data Valid.
PHY asserts RX_DV synchronously, holding it
active during the clock periods in which
RXD[3:0] contains valid data received. PHY
asserts RX_DV no later than the clock period
when it places the first nibble of the start
frame delimiter (SFD) on RXD[3:0]. If PHY
asserts RX_DV prior to the first nibble of the
SFD, then RXD[3:0] carries valid preamble
symbols. LINK_10M is shared with RX_DV
and used to convey the link status of the 10-
Mbit/s endec. The value is stored in a status
register.
PRODUCT OVERVIEW
Description
1-19