List Of Tables - Samsung S3C2501X User Manual

32-bit risc microprocessor
Table of Contents

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Table
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
S3C2501X

List of Tables

S3C2501X Signal Descriptions ...............................................................................1-12
S3C2501X Pad Type and Feature ..........................................................................1-26
S3C2501X System Configuration ...........................................................................1-27
S3C2501X Memory Controller ................................................................................1-27
S3C2501X SDRAM Controller ................................................................................1-27
S3C2501X IIC Controller ........................................................................................1-28
S3C2501X Ethernet Controller 0.............................................................................1-28
S3C2501X Ethernet Controller 1.............................................................................1-29
S3C2501X DES Controller......................................................................................1-30
S3C2501X GDMA Controller ..................................................................................1-31
S3C2501X Console UART Controller......................................................................1-32
S3C2501X High speed UART Controller.................................................................1-32
S3C2501X I/O Port Controller.................................................................................1-33
S3C2501X Interrupt Controller................................................................................1-33
S3C2501X Timer Controller....................................................................................1-34
PSR Mode. Bit Values ............................................................................................2-10
Exception Entry/Exit ...............................................................................................2-12
Exception Vectors ..................................................................................................2-14
ARM9TDMI Implementation Option........................................................................2-19
CP15 Register Map ................................................................................................2-21
ID Code Register....................................................................................................2-21
Cache Type Register Format..................................................................................2-22
CP15 Register 1 .....................................................................................................2-23
Clocking Modes......................................................................................................2-23
Cacheable Register Format....................................................................................2-24
Write Buffer Control Register .................................................................................2-25
Protection Space Register Format..........................................................................2-26
Permission Encoding..............................................................................................2-26
CP15 Data Protection Region Registers .................................................................2-27
CP15 Instruction Protection Region Registers ........................................................2-27
CP15 Protection Region Register Format ...............................................................2-28
Area Size Encoding................................................................................................2-28
Cache Operations Writing to Register 7..................................................................2-29
CP15 Register 7 Index/Segment Data Format ........................................................2-30
CP15 Register 7 Prefetch Address Format .............................................................2-30
Lockdown Register Format .....................................................................................2-31
CP15 Register 15 ...................................................................................................2-32
Title
Page
Number
xix

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