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S3C2501X
31
[1:0] Control bits for SDRAM device initialization :
00 = Normal operation
01 = Automatically issue a PALL to the SDRAM
10 = Automatically issue a MRS to the SDRAM
11 = reserved
[2] Write buffer enable:
0 = Disable merging write buffer
1 = Enable merging write buffer
[3] SDRAM controller status bit:
0 = SDRAM controller is idle
1 = SDRAM controller is busy
[31:4] Reserved
RESERVED
Figure 5-24. SDRAM Command Register
MEMORY CONTROLLER
4
3
2
1
0
I
B
B
N
U
S
Y
T
5-51
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