Des/3Des Control Register - Samsung S3C2501X User Manual

DES/3DES

8.3.1 DES/3DES CONTROL REGISTER

Bit Number
Run Enable
[0]
[1] Indata_DMA
[2] Outdata_DMA
Right_Left data
[3]
[4] Encryption or Decryption 0 = DES/3DES data will be encrypted.
[5] DES or 3DES
Encryption Mode
[6]
(ECB or CBC)
2word_req
[7]
FIFO Test
[8]
FIFO Reset
[9]
8-4
Table 8-2. DES/3DES Control Register Description
Bit Name
0 = DES/3DES disable
1 = DES/3DES enable
This bit is the same register as the Run Enable bit of the Run
Enable Register. That is, this bit has two writing address, 0x00 and
0x0C.
0 = CPU transfers the data to be encrypted from the external
memory to the DESINFIFO of DES/3DES
1 = GDMA transfers the data to be encrypted from the external
memory to the DESINFIFO of DES/3DES
0 = CPU transfers the encrypted data from the DESOUTFIFO of
DES/3DES to the external memory
1 = GDMA transfers the encrypted data from the DESOUTFIFO of
DES/3DES to the external memory
0 = CPU write(read) from left half to right half data in
DESINFIFO(out DESOUTFIFO)
1 = CPU write(read) from right half to left half data in
DESINFIFO(out DESOUTFIFO)
1 = DES/3DES data will be decrypted
0 = DES algorithm is selected
1 = Triple-DES algorithm is selected
0 = DES/3DES will be running ECB(Electronic Code Book) mode.
1 = DES/3DES will be running CBC(Cipher Block Chaining) mode.
0 = DES/3DES engine generates Valid DESOUTFIFO bit in the
state
register when DESOUTFIFO has 4 word valid data
1 = DES/3DES engine generates Valid DESOUTFIFO bit in the
state
register when DESOUTFIFO has 2 word valid data.
0 = Normal operation
1 = DESINFIFO and DESOUTFIFO test. If this bit sets to 1, user
can
scan DESINFIFO and DESOUTFIFO.
0 = Normal operation
1 = The data in the DESINFIFO and DESOUTFIFO have been
invalid data.
Description
S3C2501X