Address Mapping - Samsung S3C2501X User Manual

MEMORY CONTROLLER

5.7.3 ADDRESS MAPPING

Table 5-21. Illustrates the AHB address bus to the SDRAM address ADDR[14:0] mapping for various memory
devices when external bus width is 32 bits. Table 5-22. Illustrates the AHB address bus to the SDRAM address
ADDR[14:0] mapping for various memory devices when external bus width is 16 bits.
SDRAM
Technology
16M-bit 2Mx8
1Mx16
64M-bit 8Mx8
4Mx16
2Mx32
128M-bit 16Mx8
8Mx16
4Mx32
256M-bit 32Mx8
16Mx16
8Mx32
SDRAM
Technology
16M-bit 2Mx8
1Mx16
64M-bit 8Mx8
4Mx16
2Mx32
128M-bit 16Mx8
8Mx16
4Mx32
256M-bit 32Mx8
16Mx16
8Mx32
5-42
Table 5-21. SDRAM Address Mapping of 32-bit External Bus
14 13 12 11
* 21 * *
* 21 * *
22 21 * *
22 21 * *
22 21 * *
22 21 * *
22 21 * *
22 21 * *
22 21 * *
22 21 * *
22 21 * *
14 13 12 11
* 21 * *
* 21 * *
22 21 * 23
22 21 * 23
22 21 * *
22 21 * 23
22 21 * 23
22 21 * 23
22 21 24 23
22 21 24 23
22 21 24 23
Column Address (AddrOut[14:0])
10 9 8 7
AP * 22 9
* * 9
* 24 9
* * 9
* * 9
25 24 9
* 24 9
* * 9
26 25 9
* 25 9
* * 9
Row Address (AddrOut[14:0])
10 9 8 7
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
20 19 18 17
6 5 4 3
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
6 5 4 3
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
16 15 14 13
S3C2501X
2 1 0
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
4 3 2
2 1 0
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10
12 11 10