Samsung S3C2501X User Manual page 203

SYSTEM CONFIGURATION
Table 4-3. Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins (Continued)
CLKMOD [1:0]
2'b11 (Async)
Each PLL can also be programmed by S/W register setting. Each PLL is in pin configurable mode after the
system reset is released. You can change the PLL configuration mode to the register configurable mode by set
CPLLREN, SPLLREN, PPLLREN in the SYSCFG[31:28]. If the PLL register enable bit is set to "1, the PLL
multiplication factor is not from the external pin but from the corresponding PLLCON regiseter-CPLLCON,
SPLLCON, PPLLCON registers. The PLL is controlled by the 3 control variables, P, M ,S. When the PLL is under
the control of the S/W and the PLL control variables are dynamically changed by the S/W, the glitch may occur in
the PLL output clock. You can avoid the glitch generation by set the PLL clock enable bit, CPLLCE, SPLLCE,
PPLLCE in the SYSCFG [27:24]. When the PLL clock enable bit is set to "0" during the PLL control variable
change, the stable PLL output clock is provided. The PLL output frequency is determined as follows.
Fout = Fin × (M+8) / ((P+2) × (2^S))
Where the Fin is the frequency of the PLL input clock and the Fout is the frequency of the PLL output clock.
The four PLLs in the S3C2501X are controlled by above formula and the table 4-4 shows the PLL variables for
the most widely used frequencies.
4-12
CPU_FREQ [2:0] BUS_FREQ [2:0]
3'b110
3'b110
3'b110
3'b110
3'b110
3'b110
3'b110
3'b110
ARM940T Clock
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
Not supported
AMBA BUS Clock
Frequency Frequency
50MHz
50MHz
50MHz
50MHz
50MHz
50MHz
50MHz
50MHz
S3C2501X
133MHz
133MHz
133MHz
125MHz
100MHz
66MHz
50MHz
33MHz