Samsung S3C2501X User Manual page 88

S3C2501X
2.16.1.8 Register 7: Cache operations
A write to this register can be used to perform the following operations:
•
Flush ICache and Dcache
•
Prefetch an ICache line
•
Wait for interrupt
•
Drain the write buffer
•
Clean and flush the DCache.
The ARM940T uses a subset of the architecture V4 functions (defined in the ARM Architecture Reference
Manual). The available operations are summarized in Table 2-18 and described below.
ARM instruction
MCR p15, 0, Rd, c7, c5, 0
MCR p15, 0, Rd, c7, c5, 2
MCR p15, 0, Rd, c7, c6, 0
MCR p15, 0, Rd, c7, c6, 2
MCR p15, 0, Rd, c7, c10, 2
MCR p15, 0, Rd, c7, c13, 1
MCR p15, 0, Rd, c7, c14, 2
MCR p15, 0, Rd, c7, c8, 2
MCR p15, 0, Rd, c7, c10, 4
"Should be zero" means the value transferred in the Rd.
A read from this register returns an unpredictable value.
Table 2-18. Cache Operations Writing to Register 7
should be zero
Index/segment
should be zero
Index/segment
Index/segment
Address
Index/segment
should be zero
should be zero
Data
Flush ICache.
Flush ICache single entry.
Flush DCache.
Flush DCache single entry.
Clean DCache single entry.
Prefetch ICache line.
Clean and flush DCache single entry.
Wait for interrupt.
Drain write buffer.
PROGRAMMER' ' S MODEL
Protection region register
2-29