Introduction For Arm940T - Samsung S3C2501X User Manual

S3C2501X

2.13 INTRODUCTION FOR ARM940T

The ARM940T cached processor macrocell is a member of the ARM9 Thumb Family of high-performance 32-bit
system-on-a-chip processor solutions. It is targeted at a wide range of embedded control applications where high
performance, low system cost, small die size, and low power are key considerations.
The ARM940T processor macrocell provides a complete high performance CPU subsystem, including
ARM9TDMI RISC integer CPU, caches, write buffer, and protection unit, with an AMBA ASB bus interface.
Providing a complete high-frequency CPU subsystem frees the system-on-a-chip designer to concentrate on
design issues unique to their system.
The ARM9TDMI core within the ARM940T macrocell executes both the 32-bit ARM and 16-bit Thumb instruction
sets, allowing the user to trade off between high performance and high code density. It is binary compatible with
ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating
systems, and application software.
The ARM940T processor macrocell is designed to be integrated into larger chips. It supports EmbeddedICE
software and hardware debug and efficient production test when embedded in larger devices. The Advanced
Microcontroller Bus Architecture (AMBA) provides a high performance 32-bit System Bus (ASB) and a low power
peripheral bus (APB). The ASB is re-used to provide a channel for production test vectors with low silicon and pin
overhead. The ASB is a multi-master on-chip bus interface designed specifically to address the needs of system-
on-a-chip designs.
The EmbeddedICE software and hardware debug features of the ARM940T macrocell are accessed via a
standard 5-pin JTAG port, and are supported by ARM's Software Development Toolkit and Multi-ICE interface
hardware. The EmbeddedICE features allow software download and debug of the final production system with no
cost overhead (there is no monitor code or other use of target resident RAM or ROM).
The ARM940T processor has a Harvard cache architecture with separate 4KB instruction and 4KB data caches,
each with a 4-word line length. A protection unit allows 8 regions of memory to be defined, each with individual
cache and write buffer configurations and access permissions. The cache system is software configurable to
provide highest average performance or to meet the needs of real-time systems.
Software configurable options include:
•
Random or round robin replacement algorithm
•
Write-through or write-back cache operation (independently selectable for each memory region)
•
Cache locking with granularity 1/64 th of cache size.
Overall, the cache and write buffers improve CPU performance and minimize accesses to the AMBA bus and to
any off-chip memory, thus reducing overall system power consumption.
The ARM940T includes support for coprocessors, allowing a floating point unit or other application specific
hardware acceleration to be added.
To minimize die size and power consumption the ARM940T does not provide virtual to physical address mapping
as this is not required in most embedded applications. For systems requiring virtual memory capability, ARM
provides an alternative product, the ARM920T cached processor macrocell. The ARM940T also features a
TrackingICE mode which allows an approach similar to a conventional ICE mode of operation.
PROGRAMMER' ' S MODEL
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