Format 7: Load/Store With Register Offset; Operation - Samsung S3C2501X User Manual

S3C2501X

3.26 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET

15 14 13
0 1 0

3.26.1 OPERATION

These instructions transfer byte or word values between registers and memory. Memory addresses are pre-
indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 3-14.
L B THUMB Assembler
0 0 STR Rd, [Rb, Ro]
0 1 STRB Rd, [Rb, Ro]
1 0 LDR Rd, [Rb, Ro]
1 1 LDRB Rd, [Rb, Ro]
11 10 9
12
1 L B 0
[2:0] Source/Destination Register
[5:3] Base Register
[8:6] Offset Register
[10] Byte/Word Flag
0 = Transfer word quantity
1 = Transfer byte quantity
[11] Load/Store Flag
0 = Store to memory
1 = Load from memory
Figure 3-36. Format 7
Table 3-14. Summary of Format 7 Instructions
ARM Equivalent
STR Rd, [Rb, Ro]
STRB Rd, [Rb, Ro]
LDR Rd, [Rb, Ro]
LDRB Rd, [Rb, Ro]
8
6 5
Ro
Pre-indexed word store:
Calculate the target address by adding together the
value in Rb and the value in Ro. Store the contents of
Rd at the address.
Pre-indexed byte store:
Calculate the target address by adding together the
value in Rb and the value in Ro. Store the byte value
in Rd at the resulting address.
Pre-indexed word load:
Calculate the source address by adding together the
value in Rb and the value in Ro. Load the contents of
the address into Rd.
Pre-indexed byte load:
Calculate the source address by adding together the
value in Rb and the value in Ro. Load the byte value
at the resulting address.
INSTRUCTION SET
3 2
Rb Rd
Action
0
3-77