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2
I
C CONTROLLER
S3C2501X
Acknowledge
Acknowledge from
from receiver
transmitter
SDA by
Transmitter
MSB
SDA by
Receiver
MSB
SCL from
Master
8
9
8
9
1
2
1
2
S
P
Stop
Start
R/W
ACK
Data
ACK
Address
Condition
Condition
Figure 6-3. Master Receiver and Slave Transmitter
Even in this case, the master IC generates the timing and terminates the transfer.
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The master IC is always responsible for generating the clock signals on the I
C. Bus clock signals from a master
can only be altered by 1) a slow slave IC which "stretches" the signal by temporarily holding the clock line Low, or
2) by another master IC during arbitration.
6.4.2 GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines which are connected to a positive supply voltage through a pull-up
resistor.
2
2
When the I
C is free, the SDA and SCL lines are both high level. The output stages of I
C interfaces connected
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to the bus have an open-drain or open-collector to perform the wired-AND function. Data on the I
C can be
transferred at a rate up to 100 Kbits/s. The number of interfaces that can be connected to the bus is solely
dependent on the limiting bus capacitance of 400 pF.
6.4.3 BIT TRANSFERS
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Due to the variety of different IC's (CMOS, NMOS, and I2L, for example) which can be connected to the I
C, the
levels of logic zero (low) and logic one (high) are not fixed and depend on the associated level of V
. One clock
DD
pulse is generated for each data bit that is transferred.
6-4
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