Sdram Refresh Timer Register - Samsung S3C2501X User Manual

MEMORY CONTROLLER
5.7.9.3 Refresh Timer Register
The Refresh timer register is 32-bit read/write (some bits are read only) register. This register sets the SDRAM
refresh cycle. The refresh timer register is programmed with the number of system bus clock that should be
counted between SDRAM refresh cycles.
Registers Address
REFREG 0xF0020008
REFREG Bit
REFCYC [15:0]
[31:16]
For example, for common refresh period of 15.6us, and a system bus clock frequency of 66MHz:
-6
15.6 x 10 x 66 x 10
The refresh timer is set to 64 on reset. To ensure a refresh interval of less than 15.6us after reset, The minimum
frequency of system bus clock allowed is:
-6
64 / (15.6 x 10 )= 4.3 MHz
The refresh register should be written to as early as possible in the system start-up procedure, especially when
clock frequency is very low.
[15:0] SDRAM refresh cycle
[31:16] Reserved
5-52
Table 5-27. SDRAM Refresh Timer Register
R/W
R/W
SDRAM refresh cycle
6
= 1029
RESERVED
Figure 5-25. SDRAM Refresh Timer Register
Description
Refresh timer register
Description
Reserved
15
R/W Default value
R/W
REFCYC
S3C2501X
Reset value
0x00000020
0x00000020
0