High-Speed Uart Status Registers - Samsung S3C2501X User Manual

S3C2501X

11.3.2 HIGH-SPEED UART STATUS REGISTERS

Registers Offset Address
HUSTAT 0xF0080004
Bit Number
[0] Receive Data Valid
(RDV)
[1] Break Signal Detected
(BKD)
[2] Frame Error (FER)
[3] Parity Error (PER)
Table 11-4. High-Speed UART Status Register
R/W
R/W High-Speed UART status register
Table 11-5. High-Speed UART Status Register Description
Bit Name
This bit automatically set to one when Receive FIFO-top or
HURXBUF contains a valid data received over the serial port. The
received data can be read from Receive FIFO-top or HURXBUF .
When this bit is "0", there is no valid data.
According to the current setting of the High-Speed UART receive
mode bits, an interrupt or DMA request is generated when
HUSTAT[0]="1". In case of HUCON[3:2]="01" and
HUINT[0],interrupt requested, and HUCON[3:2]="10" or "11", DMA
request occurred.
You can clear this bit by reading Receive FIFO or HURXBUF.
NOTE: Whether Receive FIFO-top or HURXBUF depends on the
This bit automatically set to one to indicate that a break signal has
been received in Receive FIFO-top or HURXBUF.
If the BSD interrupt enable bit, HUINT[1], is "1", a interrupt is
generated when a break occurs.
You can clear this bit by writing '1' to this bit.
This bit automatically set to "1" whenever a frame error occurs
during a serial data receives operation. A frame error occurs when a
zero is detected instead of the stop bit(s).
If the FER interrupt enable bit, HUINT[2], is "1", a interrupt is
generated when a frame error occurs.
You can clear this bit by writing '1' to this bit.
This bit automatically set to "1" whenever a parity error occurs
during a serial data receives operation. If the PER interrupt enable
bit, HUINT[3], is "1", a interrupt is generated when a parity error
occurs.
You can clear this bit by writing '1' to this bit.
Description
Description
HUCON[17].
SERIAL I/O (HIGH-SPEED UART)
Reset Value
–
11-9