Samsung S3C2501X User Manual page 89

PROGRAMMER' ' S MODEL
2.16.1.8.1 Index/Segment Format
Where the required value is an index/segment, the format is:
2.16.1.8.2 ICache Prefetch Data Format
For the ICache prefetch operation, the data format is:
2.16.1.8.3 Wait for interrupt
This operation allows the ARM940T to be placed in a low-power standby mode. When the operation is invoked,
all clocks in the processor are frozen until either an interrupt or a debug request occurs. This function is invoked
by a write to register 7. The following ARM instruction causes this to occur:
MCR p15, 0, Rd, c7, c0, 4
The following instruction causes the same affect and has been added for backward compatibility with StrongARM
SA-1
MCR p15, 0, Rd, c15, c8, 2
This stalls the processor, with internal clocks held high from the time that this instruction is executed until one of
the signals nFIQ, nIRQ, or EDBGRQ is asserted. Also, if the debugger sets the debug request bit in the
EmbeddedICE unit control register, the wait-for-interrupt condition is terminated.
In the case of nFIQ and nIRQ, the processor is woken up regardless of whether the interrupts are enabled or
disabled (that is, independent of the I and F bits in the processor CPSR). The debug related waking only occurs if
DBGEN is HIGH, that is, only when debug is enabled.
If the interrupts are enabled, the ARM is guaranteed to take the interrupt before executing the instruction after the
wait-for-interrupt. If debug request is used to wake up the system, the processor will enter debug-state before
executing any further instructions.
2-30
Table 2-19. CP15 Register 7 Index/Segment Data Format
Rd bit position
31:26
25:6
5:4
3:0
Table 2-20. CP15 Register 7 Prefetch Address Format
Rd bit position
31:6
5:4
3:0
Function
Index
Should be zero
Segment
Should be zero
Function
Address bits 31:6
Cache segment
Should be zero
S3C2501X