S3C2501X
3.20 FORMAT 1: MOVE SHIFTED REGISTER
15
14
0
0
3.20.1 OPERATION
These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in
Table 3-8.
OP
THUMB Assembler
00
LSL Rd, Rs, #Offset5
01
LSR Rd, Rs, #Offset5
10
ASR Rd, Rs, #Offset5
3.20.2 INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-8. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
Examples
LSR
13
12
11
10
0
Op
[2:0] Destination Register
[5:3] Source Register
[10:6] Immediate Vale
[12:11] Opcode
0 = LSL
1 = LSR
2 = ASR
Figure 3-30. Format 1
All instructions in this group set the CPSR condition codes.
Table 3-8. Summary of Format 1 Instructions
ARM Equivalent
MOVS Rd, Rs, LSL #Offset5
MOVS Rd, Rs, LSR #Offset5
MOVS Rd, Rs, ASR #Offset5
R2, R5, #27
6
5
Offset5
NOTE
Shift Rs left by a 5-bit immediate value and
store the result in Rd.
Perform logical shift right on Rs by a 5-bit
immediate value and store the result in Rd.
Perform arithmetic shift right on Rs by a 5-bit
immediate value and store the result in Rd.
; Logical shift right the contents
; of R5 by 27 and store the result in R2.
; Set condition codes on the result.
INSTRUCTION SET
3
2
Rs
Rd
Action
0
3-67