MEMORY CONTROLLER
HCLKO
tRCSd
nRCS
nOE
ALE
DATA
tADDRd
5-34
tCOS
tALEd
tALEh
tnOEd
tMA
tDATAd
Addr
tADDRh
TACC = 0x4 (4 cycles)
TCOH = 0x1 (1 cycle)
MBE = 1 (Enable)
Figure 5-19. Read Timing Diagram (Muxed Bus)
tRCSh
tACC
tCOH
tnOEh
tDATAh
Data
Data Fetch
TCOS = 0x1 (1 cycle)
TMA = 0x2 (2 cycles)
S3C2501X