Samsung S3C2501X User Manual page 82

S3C2501X
2.16.1.3 Register 1: Control register
This contains the global control bits of the ARM940T. All reserved bits should either be written with zero or one,
as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read.
All defined bits in the control registers are set to zero at reset.
The bits in the control register have the following functions:
•
Bits 31:30
•
Bit 13
•
Bits 12 and 2
•
Bit 7
•
Bit 0
Table 2-8. CP15 Register 1
Register Bits
31 Asynchronous clocking select (iA)
30 nFastBus select (nF)
29:14 Reserved (should be zero)
13 Alternate vectors select (V)
12 ICache enable bit (1)
11:8 Reserved (should be zero)
7 Big-end bit (E)
6:3 Reserved (should be one)
2 DCache enable bit (D)
1 Reserved (should be zero)
0 Protection unit enable (P)
Control the clocking mode of the processor, as shown in Table 2-9. Clocking modes are
discussed in Chapter5 Clock Modes.
Table 2-9. Clocking Modes
Clockin Mode
FastBus mode
Reserved
Synchronous
Asynchronous
Selects the location of the vector table. During reset, the bit is cleared and the vector
table is located at address 0x00000000. When bit 13 is set, the vector table is relocated
to address 0xffff0000.
Enable the caches
Selects the endian configuration of the ARM940T. Setting bit 7 selects a big-endian
configuration. Clearing bit 7 selects a little-endian configuration. Bit 7 is cleared during
reset.
Enables the protection unit
Functions
Bit 31 Bit 30
0 0
1 0
0 1
1 1
PROGRAMMER' ' S MODEL
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