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DES/3DES
8.3.9 DES/3DES INPUT/OUTPUT DATA FIFO REGISTER
Bit Number
Bit Name
[31:0]
DESINFIFO
Bit Number
Bit Name
[31:0]
DESOUTFIFO This FIFO can be read by CPU or DMA (depends on control register value).
8-8
Table 8-14. DES/3DES Input Data FIFO Description
This FIFO can be filled by CPU or DMA (depends on control register value).
This FIFO consists of 8 words. If data are transferred by DMA, the 4-word burst
transaction(DESCON[7] is zero and DCON#[5] is one) is recommended.
Otherwise, if data are transferred by CPU, the 2-word transaction (DESCON[7]
is one is recommended. If DESCON[3] is zero, the 1
half of data to be encrypted/decrypted, bit[1:32]. The second one is the right
half of data to be encrypted/decrypted, bit[33:64]. Otherwise, if DESCON[3] is
st
one, the 1
written data is the right half of data to be encrypted/decrypted,
bit[33:64]. The second one is the left half of data to be encrypted/decrypted,
bit[1:32].
Table 8-15. DES/3DES Output Data FIFO Description
This FIFO consists of 8 words. If data are transferred by DMA, the 4-word burst
transaction(DESCON[7] is zero and DCON#[5] is one) is recommended.
Otherwise, if data are transferred by CPU, the 2-word transaction (DESCON[7]
is one is recommended. If DESCON[3] is zero, the 1
of data encrypted/decrypted, bit[1:32]. The second one is the right half of data
encrypted/decrypted, bit[33:64]. Otherwise, if DESCON[3] is one, the 1
data is the right half of data encrypted/decrypted, bit[33:64]. The second one is
the left half of data encrypted/decrypted, bit[1:32].
Description
st
written data is the left
Description
st
read data is the left half
S3C2501X
st
read
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