I 2 C Special Registers; Control Status Register - Samsung S3C2501X User Manual

2
I C CONTROLLER
2
6.5 I C SPECIAL REGISTERS
2
The I C controller has three special registers: a control status register (IICCON), a prescaler register (IICPS), and
a shift buffer register (IICBUF).
6.5.1 CONTROL STATUS REGISTER (IICCON)
The control status register for the I
Register Address
IICCON 0xF00F0000
Bit Number
[0] Buffer flag (BF)
[1] Interrupt enable (IEN)
[2] Last received bit (LRB)
[3] Acknowledge enable (ACK) The ACK bit is normally set to "1". This causes the I
[5:4] COND1, COND0
[6] Bus busy (BUSY)
[7] Reset
[31:8] Reserved
6-8
2
C, IICCON, is described in Table 6-2.
Table 6-1. Control Status Register (IICCON)
R/W
R/W

Control status register

Table 6-2. IICCON Register Description
Bit Name
The BF bit is set when the buffer is empty in transmit mode or
when the buffer is full in receive mode. To clear the buffer, you
write a "0" to this bit. The BF bit is cleared automatically
whenever the IICBUF register is written or read.
Setting the interrupt enable bit to "1" enables the I
An interrupt is generated if BF bit set to 1.
The LRB bit is read only. It holds the value of the last received bit
over the I
acknowledgement. To check for slave acknowledgement, you
test the LRB.
to send an acknowledge automatically after each byte. This bit
must be "0" when the I
and requires no further data to be received from the slave
transmitter. This causes a negative acknowledge on the I
which halts further reception from the slave device.
These bits control the generation of the start, stop, and repeat
start conditions: "00" = no effect, "01" = start, "10" = stop, and
"11" = repeat start. When start condition, BF bit should be set
simultaneously. When repeated start condition, ACK bit should
be set simultaneously
This bit is a read-only flag that indicates when the I
"1" indicates that the bus is busy. This bit is set or cleared by a
start or stop condition, respectively.
If "1" is written to the reset bit, the I
initial state.
Not applicable.
Description
Description
2
C. Normally, this bit will be the value of the slave
2
C controller is operating in receiver mode
S3C2501X
Rest Value
0x00000000
2
C interrupt.
2
C controller
2
C,
2
C is in use. A
2
C controller is reset to its