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S3C2501X
31
30 29 28
E
S
C
F
H
E
O
N
26 25
24
23 22
21
20 19
[28:15] Reserved (This bit should be cleared)
[29] Software Flow Control Enable (SFEN)
0 = Disable Software Flow Control
1 = Enable Software Flow Control
[30] Echo Test Enable (ECHO)
0 = Disable Echo Test
1 = Enable Echo Test
[31] Reserved (This bit should be cleared)
Figure 10-3. Console UART Control Register
18 17 16
15 14
13 12 11
I
W
S
R
L
T
B
SERIAL I/O (CONSOLE UART)
10
8 7 6
5
4
3
P
L
S
S
R
M
O
C
B
M
D
O
S
R
O
P
E
D
B
L
E
2
1
0
T
M
O
D
E
10-7
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