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S3C2501X
3.23 FORMAT 4: ALU OPERATIONS
15
14
13
0
0
0
3.23.1 OPERATION
The following instructions perform ALU operations on a Lo register pair.
OP
THUMB Assembler
0000 AND Rd, Rs
0001 EOR Rd, Rs
0010 LSL Rd, Rs
0011 LSR Rd, Rs
0100 ASR Rd, Rs
0101 ADC Rd, Rs
0110 SBC Rd, Rs
0111 ROR Rd, Rs
1000 TST Rd, Rs
1001 NEG Rd, Rs
1010 CMP Rd, Rs
1011 CMN Rd, Rs
1100 ORR Rd, Rs
1101 MUL Rd, Rs
1110 BIC Rd, Rs
1111 MVN Rd, Rs
11
10
9
12
0
0
0
[2:0] Source/Destination Register
[5:3] Source Register 2
[9:6] Opcode
Figure 3-33. Format 4
All instructions in this group set the CPSR condition codes
Table 3-11. Summary of Format 4 Instructions
ARM Equivalent
ANDS Rd, Rd, Rs
EORS Rd, Rd, Rs
MOVS Rd, Rd, LSL Rs
MOVS Rd, Rd, LSR Rs
MOVS Rd, Rd, ASR Rs
ADCS Rd, Rd, Rs
SBCS Rd, Rd, Rs
MOVS Rd, Rd, ROR Rs
TST Rd, Rs
RSBS Rd, Rs, #0
CMP Rd, Rs
CMN Rd, Rs
ORRS Rd, Rd, Rs
MULS Rd, Rs, Rd
BICS Rd, Rd, Rs
MVNS Rd, Rs
6
5
Op
NOTE
Rd: = Rd AND Rs
Rd: = Rd EOR Rs
Rd : = Rd << Rs
Rd : = Rd >> Rs
Rd : = Rd ASR Rs
Rd : = Rd + Rs + C-bit
Rd : = Rd - Rs - NOT C-bit
Rd : = Rd ROR Rs
Set condition codes on Rd AND Rs
Rd = - Rs
Set condition codes on Rd - Rs
Set condition codes on Rd + Rs
Rd: = Rd OR Rs
Rd: = Rs * Rd
Rd: = Rd AND NOT Rs
Rd: = NOT Rs
INSTRUCTION SET
3
2
Rs
Rd
Action
0
3-71
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