Samsung S3C2501X User Manual page 265

MEMORY CONTROLLER
5.7.9.2 Command Register
The configuration register 1 is 32-bit read/write (some bits are read only) register. The SDRAM initialization
command, write buffer operation can be controlled by this register.
Registers Address
CMDREG 0xF0020004
CMDREG Bit
INIT [1:0]
WBUF [2]
BUSY [3]
[31:4]
NOTE: WBUF field of configuration register is a read-only bit if write buffers are not included in an AHB interface sub-block
5-50
Table 5-26. SDRAM Command Register
R/W
R/W
Description
Control bits for SDRAM device initialization
00 = Normal operation
01 = Automatically issue a PALL to the SDRAM
10 = Automatically issue a MRS to the SDRAM
11 = reserved
Write buffer enable
0 = Disable merging write buffer
1 = Enable merging write buffer
NOTE: Disabling the write buffer will flush any stored
value(s) to the external SDRAM memory
SDRAM controller status bit
0 = SDRAM controller is idle
1 = SDRAM controller is busy
Reserved
Description
SDRAM command register
S3C2501X
Reset value
0x00000000
R/W Default value
R/W 00
R/W 0
R 0