Samsung S3C2501X User Manual page 225

MEMORY CONTROLLER
Table 5-9 and 5-10.
Using little-endian and word access, Program/Data path between register and external memory.
WA=Address whose LSB is 0, 4, 8, C, EA=External Address
HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E
BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
X=Don't care
Table 5-9. External 32-bit Datawidth Store Operation with Little-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External DATA
Timing Sequence
Table 5-10. External 32-bit Datawidth Load Operation with Little-Endian
Transfer Width
Bit Num.
CPU Register Data
CPU Address
Bit Num.
CPU Data Bus
External Address (ADDR)
Bit Num.
External DATA
Timing Sequence
5-10
STORE (CPU Reg → → External Memory)
32-bit 16-bit
31 0 31 0
abcd xxcd
WA HA
31 0 31 0
abcd cdcd
31 0 31 0
abcd xxcd
LOAD (CPU Reg ← ← External Memory)
32-bit 16-bit
31 0 31 0
abcd xxcd
WA HA
31 0 31 0
abcd cdcd
31 0 31 0
abcd abcd
31 0 31 0
xxab xxxd
HA+1 BA
31 0 31 0
abab dddd
EA
31 0 31 0
abxx xxxd
31 0 31 0
xxab xxxd
HA+1 BA
31 0 31 0
abab dddd
EA
8-bit
31 0 31 0
xxxc xxxb
BA+1 BA+2
31 0 31 0
cccc bbbb
31 0 31 0
xxcx xbxx
8-bit
31 0 31 0
xxxc xxxb
BA+1 BA+2
31 0 31 0
cccc bbbb
31 0
abcd
S3C2501X
31 0
xxxa
BA+3
31 0
aaaa
31 0
axxx
31 0
xxxa
BA+3
31 0
aaaa